A Failure Mode Analysis of a 6-bit Folding ADCs
نویسندگان
چکیده
For next generation mixed signal ICs, the integration of Design-for-Testability and Built-In Self-Test structures is expected to be of crucial importance for satisfying quality and economic demands. The judgment and evaluation of such testability optimisations, however, requires a better understanding of circuit specific failure modes in deep sub-micron technologies. This paper presents fault simulation results for a 6-bit folding ADC carried out to identify key failure modes and extract its test requirements.
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